Sponsorship Levels Template UTOSS' 5-stage pipelined RISC-V core with synchronous memory support. Icon For Product Launch
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. ├── src -------------------------- contains core's source modules │ ├── utoss_riscv.sv ----------- our core's top module │ ├── headers/ │ ├── interfaces/ │ ├── modules/ ----------------- core modules │ ├── packages/ │ ├── stages/ ------------------ stage implementations │ ├── utils/ │ └── ext/ --------------------- extension modules ├── test ------------------------- contains our SystemVerilog testbenches │ └── vcd ---------------------- contains VCD file outputs generated by the testbenches ├── build ------------------------ contains intermediary verilator artifacts ├── out -------------------------- contains verilator builds for testbenches and core module ├── riscof ----------------------- contains RISCOF-related files and scripts; we use this framework │ for compiance testing, to make sure our core behaves as defined │ by the ISA specification; check out the corresponding wiki page │ here for more details: ├── envs ------------------------- contains execution environments to connect our core to platforms | | for simulation and testing │ ├── de1-soc ------------------ one of the platforms we support; DE1-SoC is an FPGA board with a │ │ bunch of peritherals commonly used for digital design courses at │ │ the University of Toronto; check-out corresponding wiki page here | | for more details: │ └── simulation --------------- abstract platform implementation we use for testing │ ├── MA.sv ---------------- memory peripheral implementation │ └── top.sv --------------- instantiates our core and its peripherals ├── Makefile --------------------- top-level build targets/scripts declarations ├── README.md -------------------- this file ├── svlint.toml ------------------ project-wide config for linting SystemVerilog code ├── Dockerfile.ci ---------------- image for CI pipeline with all necessary dependencies ├── Dockerfile.riscv-toolchain --- sidekick image that builds RISC-V toolchain from source └── Dockerfile.quartus ----------- sidekick image that installs Quartus Prime Lite Transferring Credit Card Debt To Another Card Put new modules into src/ folder. Welcome To The Team Word Document Template
Instagram Story Promoting Post We use SVLint to make sure our SystemVerilog code is well formatted. Use the following command to check for new offences: News Article Website Template
$ make svlint Business Card Maker Templates It is important that new functionality is tested to a reasonable extent by using test benches. To run all existing testbenches use make run_tb Basic Marketing Plan Example
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$ make new_tb name="something" Medium Article Promotion If you are on Windows, create a new testbench file in test/ folder named something_tb.sv (the _tb.sv suffix and extension are necessary for the test suite to recognize this file as a testbench). Copy the content of test/tb_template.sv.m4 into your newly-created testbench file and start writing the test bench. Cool Things To Snap